The present invention relates to semiconductor packaging, and more particularly, to attaching a semiconductor die in a device package.
Semiconductor devices are typically fabricated on thin wafers of silicon. Several dice are produced on each wafer, with each die representing a single semiconductor device. Each die on a wafer is tested for gross functionality, and sorted according to whether the die passes or fails the gross functionality test. After being sorted according to gross functionality, the wafers are cut using a wafer saw, and the individual die are singulated. The die determined to be non-functional are scrapped. The functional die are packaged and further tested to ensure that each packaged device satisfies a minimum level of performance. Typically, the functional devices are permanently packaged by encapsulating the die in a plastic package. Packaging of the functional devices facilitates handling of the devices and also protects the die from damage during the manufacture of circuits using the packaged devices.
There are several conventional structures and methods for packaging singulated die. For example, more common package types include small outline j-bend (SOJ) packages, thin small outline packages (TSOP), and zigzag in-line packages (ZIP). The finished packaged devices are often mounted onto a substrate to form a module. A singulated die is packaged in the aforementioned package types by attaching the die to a lead frame paddle and electrically coupling exposed bond pads of the die to metal leads. The lead frame, die, and a portion of the metal leads are subsequently encapsulated by a plastic resin to protect the integrated circuit from damage. The encapsulated device is then trimmed from the lead frame and the metal leads formed to the correct shape.
An alternative lead frame structure, known as lead on chip (LOC) may be employed instead of the structure having a lead frame paddle. In an LOC structure, individual metal leads are typically attached to the surface of the die using double-sided adhesive tape having a polyimide base coated on both sides with adhesive material. The metal leads and die are then heated to attach to the adhesive material. The bond pads of the semiconductor die are subsequently wire bonded to a respective metal lead to electrically connect the semiconductor die to receive electrical signals applied to the conductive leads. The LOC lead frame and die are then encapsulated in a plastic resin, then followed by a trim and form process. The LOC structure and packaging process are described in U.S. Pat. No. 4,862,245 to Pashby et al., issued Aug. 29, 1989, and U.S. Pat. No. 4,916,519 to Ward, issued Apr. 10, 1990, which are incorporated herein by reference.
Recently, semiconductor manufacturers have developed a package structure where unpackaged die are mounted directly onto a substrate, for example, a printed circuit board, thus allowing modules to be designed with increased device density. Examples of these types of packages structures include ball grid array (BGA) packages, and other chip scale packages (CSP) having package dimensions that are slightly larger than the dimension of the encapsulated die. The die is mounted onto the substrate and is electrically coupled to conductive traces formed on the substrate by wire bonding the bond pads of the die. Alternatively, the conductive traces and the bond pads may be electrically coupled by using tape automated bonded (TAB) wire instead. The resulting structure is subsequently, partially or entirely, encapsulated to protect the device from damage. External leads, often in the form of solder balls, are then attached to attachment sites on the conductive traces so that the integrated circuit fabricated on the die may be electrically contacted through the external leads.
Following packaging, the device is typically mounted onto a printed circuit board (PCB) as a component in a larger electronic system. Conductive pads on the PCB are positioned to correspond to the location of the external leads of the packaged device. The packaged device is positioned accordingly onto the conductive pads and subjected to a reflow process at an elevated temperature in order to solder the packaged device to the PCB. In the case of a BGA type package, the solder is provided by the solder balls of the completed package.
After the solder has cooled, the packaged device is rigidly attached to the PCB. However, there may be an issue with regards to the reliability of the solder joints as a result of the different expansion rates of the semiconductor die of the packaged device and the PCB to which the packaged device is soldered. The coefficient of thermal expansion (CTE) of the die is typically much lower than that for the PCB. Thus, when the electronic system reaches its operating temperature, the PCB will expand more than the die. The thermal mismatch results in a shearing stress focused at the interface between the packaged device and the PCB, namely, the solder joints. The reliability of the electronic system is compromised when the thermal mismatch stress applied to the solder joints of the packaged device is great enough to cause one of the solder joints to fail.
One method that has been used to alleviate some of the thermal mismatch stress at the solder joint is using a package structure where the die is attached to a flexible substrate using a compliant elastomer pad. Upon reaching operating temperature, the PCB will expand and laterally shift the position of the contact pads with respect to the die. The compliant nature of the elastomer pad allows the solder balls of the packaged device to shift laterally with the expanding PCB. Thus, the different expansion rates of the die in the packaged device, and the PCB to which the packaged device is soldered, is accommodated by the flexible elastomer pad attaching the die to the flexible substrate. However, in the case where TAB wire connections are used in such a package structure to electrically couple the bond pads of the die to the conductive traces of the substrate, thermal expansion of the elastomer pad creates reliability problems for the packaged device itself. It has been shown in reliability testing that the TAB wire joint is the point most susceptible to failure when the packaged device is subjected to temperature cycle tests (e.g., xe2x88x9265xc2x0 C. to +150xc2x0 C.) or high temperature and humidity tests (e.g., 85xc2x0 C., 85% RH, alternating bias). Thermal expansion of the elastomer pad laterally shifts the position of the flexible substrate relative to the bond pads of the die. Consequently, the resulting compliant structure places stress at the TAB wire joint where the wire is bonded to the bond pad of the die.
Another method that has been used to minimize thermal mismatch stress between the die and the PCB is to attach the die to a flexible substrate with elastomer posts. One example of this type package is a product developed by Tessera called xcexcBGA(copyright). Viscous elastomer material is screen printed onto the flexible substrate and cured to form the elastomer posts. A dry or wet die attach adhesive is then applied to the end of the cured elastomer in order to attach the die to the elastomer posts. Subsequently, the bond pads of the die are electrically coupled to the conductive traces of the flexible substrate by a TAB wiring process. Although the resulting compliant structure accommodates the different expansion rates of the die and the PCB, the assembly process is time-consuming. Additional assembly steps are required to screen print the viscous elastomer material onto the flexible substrate, to cure the viscous material, and to apply the dry adhesive to the resulting elastomer post. As a result, product throughput at the assembly stage is reduced.
Furthermore, attaching the die to the substrate using elastomer posts requires precision processing to maintain assembly yields. In typical CSP type packages, coplanarity of the die and the substrate should be maintained to ensure that all solder balls contact the PCB upon reflow. Thus, the height of the elastomer posts should be substantially the same in order to achieve the required coplanarity. However, precision processing and equipment is required to achieve this level of consistency. Variations in the screen printing process or in the attachment of dry adhesive to the elastomer posts may result in unacceptable coplanarity, and consequently, unacceptable packaged devices.
Therefore, there is the need for a method and structure for a semiconductor package that can alleviate thermal mismatch stress without compromising the reliability of the package structure or adding several additional process steps.
The present invention is directed to a high reliability semiconductor package structure. The package structure is a ball grid array type package that uses a plurality of pieces of adhesive film to attach a semiconductor die to a substrate having conductive traces in order to alleviate thermal mismatch stress between the semiconductor die and the printed circuit board to which the packaged device is soldered, while maintaining the reliability of the packaged device itself.